Generally, digital circuitry requires at least a specified minimum voltage to properly operate in a given mode. For example, for static random access memory (SRAM) to accurately maintain data stored within a SRAM cell during a retention mode, a minimum retention voltage is necessary. If the retention voltage drops below the minimum, the data stored in the SRAM risks being corrupted such that the stored data may be lost. Conventional circuits have addressed this issue, but each circuit design has its own disadvantages.
Conventional voltage generation circuits generally implement analog circuitry to provide a retention voltage. One known circuit employs two PMOS transistors coupled together to effectively form a diode in a retention mode. However, as technology sizes decrease and as power levels decrease, the voltage drop across the formed diode in the retention mode may be a limiting or preventative factor. For example, if the operating voltage of a system is 0.7 volts and a SRAM requires 0.5 volts in retention mode, but the voltage drop across the formed diode is 0.3 volts, then the voltage generation circuit would not provide an adequate retention voltage to the SRAM during the retention mode because the operation voltage of 0.7 volts minus the voltage drop of the diode of 0.3 volts would result in at most a generated retention voltage of 0.4 volts which is less than the required minimum.
A second known circuit uses an operational amplifier and a feedback loop to regulate the generated retention voltage. However, the use of the operational amplifier typically continually consumes power during the retention mode. Thus, the operational amplifier may consume large amounts of power in this mode.
Accordingly, there is a need in the art to overcome or obviate these stated deficiencies of the convention voltage generation circuits.